1. Field of the Invention
The present invention relates to an integrated circuit having a standard cell array that programmably includes spare logic gates.
2. Description of the Related Art
The cost of making an integrated circuit (IC) is related to the number and lithography size of processing steps: necessary for forming the desired circuit pattern, including active devices (e.g., transistors) and associated interconnections. These steps include those necessary for obtaining a substrate, typically a semiconductor, and forming multiple dopant diffusions, insulating regions, and conductive patterns in and on the substrate. These forming steps include multiple lithography steps, wherein the size, shape, and location of the various features are defined. In present-day commercial integrated circuit production, a minimum lithography linewidth of 0.25 micrometers (xe2x80x9cmicronsxe2x80x9d) is typically employed, with a reduction to 0.18 microns likely in the near future, and subsequent reductions in due course thereafter. This advanced processing technology allows for the production of very complex integrated circuits often employing over a million transistors, and even greater than 10 million transistors in many cases. The functions that may be implemented thereby are also often very complex.
The process of designing an integrated circuit must not only implement the desired circuit functionality (i.e., circuit synthesis), but must also translate that functionality into the precise location and geometry of the above-noted features on the integrated circuit (i.e., layout). Unfortunately, the very great complexity in the synthesis and layout of an integrated circuit usually results in a number of design errors that must be corrected before the IC functions satisfactorily. This is true even though the actual number of errors may be relatively small, being typically only a few logic gates out of several thousand or more. That is, the error rate is often significantly less than 20 percent of the total number of gates on the IC, and typically about 5 percent, and yet the errors must be corrected. To correct these mistakes, it is often necessary to construct an entirely new set of lithographic masks that are used to define the above-noted features. In typical IC production processes, a mask set usually comprises at least twelve masks, and frequently twenty or more, at a cost of over 100 thousand dollars per mask set. One common form of integrated circuit is an xe2x80x9cApplication Specific Integrated Circuitxe2x80x9d (ASIC), that implements a desired function,using an array of xe2x80x9cstandard cells. Standard cell design is commonly implemented by a set: of standard functions or physical cells that taken as a group are called a library. The individual cells within the library implement discrete gate-level function; for example, NAND, NOR, XOR, ADD, invert, multiplex, register, latch, driver, etc.
Standard cell layout is distinguished by custom transistor layout, so that a change to a physical cell location or type requires all mask levels to be changed, with the attendant costs. Physically, standard cell layout places individual cells into cell rows, with cells typically (but not necessarily) all being the same height. The rows may be separated by wiring channels in which signal conductors are placed. Alternatively, the rows may be abutted in which case the wiring channels are omitted. Standard cell designs, often referred to as Application Specific Integrated Circuits (ASICs) typically offer the IC industry the best combination of various factors, including a relatively short design interval, productivity, cost, die size, power and performance. However, a significant drawback is the time and cost required to make changes to the logic circuitry after the IC is initially designed. In addition, it is very difficult to exhaustively test ASIC designs of the above-noted complexity before mask order. It is known in the ASIC art to include extra standard cells in a row that are not fully connected in the initial design, but are available for making minor changes in subsequent mask revisions. However, that prior-art technique requires programming all the metal levels in order to include the extra cells in the functional circuitry. Consequently, a need exists to be able to introduce minor design changes into an ASIC after the initial design without requiring a redesign of all the mask levels.
Furthermore, the prior-art technique may exact a performance penalty if a needed cell type is far from the needed location. That is, the specific cells available and their locations are commonly not optimal for the design change required. This is due to the uncontrolled spare gate placement resulting from netlist-based methods of the cell placement engine. That is because netlist-based standard cell spare gates are placed by the cell placement engine in the place-and-route tool, resulting in pseudo-random placement of spare gates. Another commonly encountered drawback is that specific design changes, for example adding a 32-bit shift register to the design, exceed the capacity of the spare gates local to the region of interest. In addition, the fixed spare gates may be of an unsuitable gate type.
In the art of circuit board design, it is known to make small changes to system functionality by tacking on individual wires and gates to patch a design as needed. This may be referred to as the xe2x80x9cwhite wirexe2x80x9d approach to circuit modifications. However, this utilizes the ability to solder individual wires to the circuit board, and in any direction necessary. In other words, various portions of the circuit may be accessed after the initial design, which capability is not available in integrated circuits. Therefore, in the case of integrated circuits, other techniques have been adopted to change circuit functionality. For example, various forms of programmable logic are known in the art. One form is the xe2x80x9cfield programmable gate arrayxe2x80x9d (FPGA), in which various logic configurations may be selected in a board-mounted integrated circuit by the use of software-controlled logic gates and routing conductors; see, for example U. S. Pat. No. 5,384,497 co-assigned herewith. In another variation, electrically blown-fuses are used for programming the FPGA in the field; i.e., after manufacture. However, in return for the flexibility of programming, FPGAs tends to be slower than the ASIC equivalent. In addition, FPGAs are not as dense, typically one-tenth the density of ASICs or less, so they are more costly.
Another form of programmable logic is the gate array, which use a fixed pattern of transistors upon which logic cells. are programmed by means of custom layout of the metal conductor levels. A change in a gate array typically requires changing all of the metal mask levels. Since gate arrays rebuild all of the wiring, the design interval required to make a change in the logic is lengthy and costly. For example, in a 6-level metal technology the time interval for a gate array redesign is typically over one-half that of a standard cell redesign. Furthermore, the density of a gate is array is only about one-half that of a standard cell design. The speed of the gates in a gate array is similar to those in an ASIC, but the overall logic speed, is usually about 10 to 20 percent slower due to less efficient signal routes. Still another type of programmable device employs a laser-configurable or single-mask configurable gate array that is useful for prototyping, and which may be densified into a fixed compact design for volume production; see U.S. Pat. No. 95,565,758.
Some attempts have been made to mix technologies at the functional block level, with a block typically comprising over 1,000 gates. All the gates in a given functional block are of a given technology (e.g,., standard cell or gate array). The strategy is to implement the less defined and hence less stable logic in the more configurable technologies, and to implement the stable logic in standard cells. The result is a combination of discrete functional blocks implemented in several technology forms. However, the block-based technology mixes impose a requirement to separate the logic into different technology-based blocks with relatively long wiring between blocks. This adds extra effort to the design itself and compromises performance due to the long interblock wires. In addition, these prior-art designs do not provide for reprogrammability to alter the standard-cell portions of the logic, often the major portion of the IC""s logic, while providing for economical volume production.
I have invented an integrated circuit comprising an array of standard cell logic having included therein spare gate logic. The spare gates are connectable to at least some of the standard cells in the array through an array of vias that elevate lower level conductors up to an intermediate conductor level. The logic of an integrated circuit design may then be changed by changing the pattern of the upper level conductors.